1 ? hsp45102 12-bit numerically c ontrolled oscillator the intersil hsp45102 is numerically controlled oscillator (nco12) with 32-bit frequency re solution and 12-bit output. with over 69db of spurious free dynamic range and worst case frequency resolution of 0.009hz, the nco12 provides significant accuracy for freque ncy synthesis solutions at a competitive price. the frequency to be generated is selected from two frequency control words. a single control pin selects which word is used to determine the output frequency. switching from one frequency to another occurs in one clock cycle, with a 6 clock pipeline delay from the time that the new control word is loaded until t 3- he new frequency appears on the output. two pins, p0-1, are provided for phase modulation. they are encoded and added to the top two bits of the phase accumulator to offset the phase in 90 increments. the 13-bit output of the phase offset adder is mapped to the sine wave amplitude via the sine rom. the output data format is offset binary to simplify interfacing to d/a converters. spurious frequen cy components in the output sinusoid are less than -69dbc. the nco12 has applications as a direct digital synthesizer and modulator in low cost digital radios, satellite terminals, and function generators. features ? 33mhz, 40mhz versions ? 32-bit frequency control ? bfsk, qpsk modulation ? serial frequency load ? 12-bit sine output ? offset binary output format ? 0.009hz tuning resolution at 40mhz ? spurious frequency components <-69dbc ? fully static cmos ?low cost applications ? direct digital synthesis ? modulation ? psk communications ? related products - hi5731 12-bit, 100mhz d/a converter block diagram ordering information part number temp. range (c) package pkg. dwg. # HSP45102PC-33 0 to 70 28 ld pdip e28.6 hsp45102sc-33 0 to 70 28 ld soic m28.3 hsp45102sc-40 0 to 70 28 ld soic m28.3 hsp45102si-33 -40 to 85 28 ld soic m28.3 hsp45102si-3396 28 ld soic tape and reel m28.3 phase accumulator frequency control section phase offset adder sine rom clk po-1 32 32 13 out0-11 msb/lsb sften sd sclk load txfr sel_l/m enphac 13 12 data sheet july 2004 fn2810.7 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 1999, 2004. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 pinout 28 lead pdip, 28 lead soic top view pin description name type description v cc +5v power supply pin. gnd ground p0-1 i phase modulation inputs (bec ome active after a pipeline delay of f our clocks). a phase shift of 0, 90, 180, or 270 degrees can be selected as shown in table 1. clk i nco clock. (cmos level) sclk i this pin clocks the frequenc y control shift register. sel_l/ m i a high on this input selects the least significant 32 bi ts of the 64-bit frequency register as the input to the phase accumulator; a low selects the most significant 32 bits. sften i the active low input enables the shifting of the frequency register. msb/ lsb i this input selects the shift direction of the frequency r egister. a low on this input shifts in the data lsb first; a high shifts in the data msb first. enphac i this pin, when low, enables the clocking of the phas e accumulator. this input has a pipeline delay of four clocks. sd i data on this pin is shifted into the frequency register by the rising edge of sclk when sften is low. txfr i this active low input is clocked ont o the chip by clk and becomes acti ve after a pipeline delay of four clocks. when low, the frequency control word selected by sel_l/ m is transferred from the frequency register to the phase accumulator?s input register. load i this input becomes active after a pipeline delay of five clocks. when low, the feedback in the phase accumulator is zeroed. out0-11 o output data. out0 is lsb. unsigned. all inputs are ttl level, with the exception of clk. overline designates active low signals. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 out6 out7 out8 out9 out10 out11 gnd v cc sel_l/m sften msb/lsb enphac sd sclk 2 3 4 5 6 7 8 9 10 11 12 13 14 out5 out3 out2 out1 out0 gnd p1 load txfr clk gnd out4 v cc p0 1 hsp45102
3 functional description the nco12 produces a 12-bit sinusoid whose frequency and phase are digitally controlled. the frequency of the sine wave is determined by one of two 32-bit words. selection of the active word is made by sel_l / m . the phase of the output is controlled by the two- bit input p0-1, which is used to select a phase offset of 0, 90, 180, or 270 degrees. as shown in the block diagr am, the nco12 consists of a frequency control section, a phase accumulator, a phase offset adder and a sine rom. the frequency control section serially loads the frequency control word into the frequency register. the phase accumulator and phase offset adder compute the phase angle using the frequency control word and the two phase modulation inputs. the sine rom generates the sine of the computed phase angle. the format of the 12-bit output is offset binary. frequency control section the frequency control section shown in figure 1 serially loads the frequency data into a 64-bit, bidirectional shift register. the shift direction is selected with the msb/ lsb input. when this input is high, the frequency control word on the sd input is shifted into the register msb first. when msb/ lsb is low the data is shifted in lsb first. the register shifts on the rising edge of sclk when sften is low. the timing of these signals is shown in figures 2a and 2b. the 64 bits of the frequency r egister are sent to the phase accumulator section where 32 bits are selected to control the frequency of the sinusoidal output. phase accumulator section the phase accumulator and phase offset adder compute the phase of the sine wave from the frequency control word and the phase modulation bits p0-1. the architecture is shown in figure 1. the most significant 13 bits of the 32-bit phase accumulator are summed with the two-bit phase offset to generate the 13-bit phase input to the sine rom. a value of 0 corresponds to 0 o , a value of 1000 hexadecimal corresponds to a value of 180 o . the phase accumulator advances the phase by the amount programmed into the frequency control register. the output frequency is equal to: where n is the 32 bits of fr equency control word that is programmed. int[?] is the int eger of the computation. for example, if the control word is 20000000 hexadecimal and the clock frequency is 30mhz, th en the output frequency would be f clk /8, or 3.75mhz. the frequency control multiplexer selects the least significant 32 bits from the 64- bit frequency control register when sel_l / m is high, and the most significant 32 bits when sel_l / m is low. when only one frequency word is desired, sel_l / m and msb/ lsb must be either both high or both low. this is due to the fact that when a frequency control word is loaded into th e shift register lsb first, it enters through the most significa nt bit of the register. after 32 bits have been shifted in, t hey will reside in the 32 most significant bits of the 64-bit register. when txfr is asserted, the 32 bits selected by the frequency control multiplexer are clocked into the phase accumulator / 13 msbs r.p0-1 clk p0-1 clk / 32 r e g r e g / 32 / 32 / 32 accumulator input register a d d e r r.txfr / 32 clk / 32 ?0? / 32 64-bit shift reg / 32 / 32 phase accumulator 2-dly r e g r e g r.p0-1 phase offset adder / 13 a d d e r / 13 r e g sine rom / 12 clk clk frctrl frctrl sd sclk frequency control section r.load sften msb/lsb r.enphac r.txfr r.load txfr load sel_l/m r.enphac 0-31 32-63 (high selects frctrl0-31, low selects frctrl32-63) out0-11 4-dly r e g enphac figure 1. nco-12 functional block diagram r e g clk 0 1 mux 0 1 mux f lo nf clk 2 32 ? () , or = (eq. 1) n int f out f clk --------------- ?? ?? ?? 2 32 , = (eq. 2) hsp45102
4 input register. at each clock, the contents of this register are summed with the current contents of the accumulator to step to the new phase. the phase accumulator stepping may be inhibited by holding enphac high. the phase accumulator may be loaded with the value in the input register by asserting load , which zeroes the feedback to the phase accumulator. the phase adder sums the encoded phase modulation bits p0-1 and the output of the phase accumulator to offset the phase by 0, 90, 180 or 270 degrees. the two bits are encoded to produce the phase mapping shown in table 1. this phase mapping is provided for direct connection to the in-phase and quadrature data bi ts for qpsk modulation. rom section the rom section generates the 12-bit sine value from the 13-bit output of the phase adde r. the output form at is offset binary and ranges from 001 to fff hexadecimal, centered around 800 hexadecimal. table 1. phase mapping p0-1 coding p1 p0 phase shift (degrees) 0 0 0 0 1 90 1 0 270 1 1 180 figure 2a. frequency loading enabled by sften figure 2b. frequency loading controlled by sclk figure 3. i/o timing sclk sd sften msb/lsb 0 1 2 63 62 61 sclk sd sften msb/lsb 0 1 2 63 62 61 clk load txfr out0-11 1 3 4 6 7 8 9 10 11 5 2 new data enphac sel_l/m hsp45102
5 absolute maxi mum ratings t a = 25c thermal information supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0v input, output or i/o voltage applied . . . . . gnd -0.5v to v cc +0.5v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions operating voltage range (commercial, industrial) . . +4.75v to +5.25v operating temperature range (commercial) . . . . . . . . 0c to 70c operating temperature range (industrial) . . . . . . . . .-40c to 85c thermal resistance (typical, note 1) ja (c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . -65c to 150c lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . 300c (soic - lead tips only) die characteristics backside potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v cc caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. dc electrical specifications parameter symbol test conditions min max units logical one input voltage v ih v cc = 5.25v 2.0 - v logical zero input voltage v il v cc = 4.75v - 0.8 v high level clock input v ihc v cc = 5.25v 3.0 - v low level clock input v ilc v cc = 4.75v - 0.8 v output high voltage v oh i oh = -400 a, v cc = 4.75v 2.6 - v output low voltage v ol i ol = +2.0ma, v cc = 4.75v - 0.4 v input leakage current i i v in = v cc or gnd, v cc = 5.25v -10 10 a standby power supply current i ccsb v in = v cc or gnd, v cc = 5.25v, note 4 - 500 a operating power supply current i ccop f = 33mhz, v in = v cc or gnd v cc = 5.25v, notes 2 and 4 - 99 ma capacitance t a = 25c, note 3 parameter symbol test conditions min max units input capacitance c in freq = 1mhz, v cc = open. all measure - ments are referenced to device ground - 10 pf output capacitance c o - 10 pf notes: 2. power supply current is proportional to operating frequency. typical rating for i ccop is 3ma/mhz. 3. not tested, but characterized at initial design and at major process/design changes. 4. output load per test load circuit with switch open and c l = 40pf. hsp45102
6 ac test load circuit ac electrical specifications v cc = 5.0v 5%, t a = 0c to 70c, t a = -40c to 85c (note 5) parameter symbol notes -33 (33mhz) -40 (40mhz) units min max min max clock period t cp 30 - 25 - ns clock high t ch 12 - 10 - ns clock low t cl 12 - 10 - ns sclk high/low t sw 12 - 10 - ns setup time sd to sclk going high t ds 12 - 12 - ns hold time sd from sclk going high t dh 0 - 0 - ns setup time sften , msb/ lsb to sclk going high t ms 15 - 12 - ns hold time sften , ms b/ l sb from sclk going high t mh 0 - 0 - ns setup time sclk high to clk going high t ss note 6 16 - 15 - ns setup time p0-1 to clk going high t ps 15 - 12 - ns hold time p0-1 from clk going high t ph 1 - 1 - ns setup time load , txfr , enphac , sel_l/ m to clk going high t es 15 - 13 - ns hold time load , txfr , enphac , sel_l/ m from clk going high t eh 1 - 1 - ns clk to output delay t oh 2 15 2 13 ns output rise, fall time t rf note 7 8 - 8 - ns notes: 5. ac testing is performed as follows: input levels (clk input) 4.0v and 0v; input levels (all other inputs) 0v and 3.0v; timing r eference levels (clk) 2.0v; all others 1.5v. output load pe r test load circuit with switch closed and c l = 40pf. output transition is measured at v oh > 1.5v and v ol < 1.5v. 6. if txfr is active, care must be taken to not violate setup and hold ti mes as data from the shift registers may not have settled before clk occurs. 7. controlled via design or process parameters and not directly te sted. characterized upon initial design and after major process and/or design changes. equivalent circuit c l (note) i oh 1.5v i ol dut switch s1 open for i ccsb and i ccop s 1 note: test head capacitance. hsp45102
3-7 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com waveforms figure 4. t cp t cl t ch t ps t ph t es t eh t oh t rf t sw t ss t ds t dh t mh t ms t sw clk sclk sd msb/lsb , p0-1 out0-11 enphac , sel_l/m load , txfr , sften hsp45102
|
